Signed

Signed vs. Unsigned in VHDL

All Digital Designers must understand how math works inside of an FPGA or ASIC. The first footstep to that is agreement how signed and unsigned signal types piece of work. Signed and unsigned types exist in the numeric_std packet, which is part of the ieee library. It should exist noted that there is some other package file that is used frequently to perform mathematical operations: std_logic_arith. However, std_logic_arith is not an official ieee supported bundle file and it is non recommended for use in digital designs.

A bespeak that is defined as type signed ways that the tools interpret this signal to be either positive or negative. A bespeak that is defined as type unsigned means that the bespeak will be only positive. Internally, the FPGA will use Ii's Complement representation. For example, a 3-chip signal can be interpreted according to the table below:

$.25	Unsigned Value	Signed Value
011	three	3
010	2	2
001	1	i
000	0	0
111	vii	-1
110	6	-2
101	five	-3
100	4	-four

Are y'all dislocated yet? Y'all should be, this is not intuitive! Let's look at an example which will hopefully clear things up. The file below tests out how signed unsigned works. What needs to be understood is that whether or not the signals are defined as signed or unsigned does not touch on how the actual binary math is performed.

For example: For two signed vectors 10001 + 00010 the answer is still 10011, Merely information technology's the interpretation of the event that is different.
For the unsigned case, the answer (10011) represents 19.
For the signed case, the answer (10011) represents -thirteen.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity signed_unsigned is   port (     i_rst_l : in std_logic;     i_clk   : in std_logic;     i_a     : in std_logic_vector(four downto 0);     i_b     : in std_logic_vector(4 downto 0)     ); end signed_unsigned;  compages behave of signed_unsigned is   signal rs_SUM_RESULT : signed(4 downto 0)   := (others => '0');   betoken ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0');   signal rs_SUB_RESULT : signed(4 downto 0)   := (others => '0');   signal ru_SUB_RESULT : unsigned(4 downto 0) := (others => '0');          begin    -- Purpose: Add together two numbers.  Does both the signed and unsigned   -- addition for demonstration.  This process is synthesizable.   p_SUM : procedure (i_clk, i_rst_l)   begin      if i_rst_l = '0' then             -- asynchronous reset (active low)       rs_SUM_RESULT <= (others => '0');       ru_SUM_RESULT <= (others => '0');     elsif rising_edge(i_clk) then              ru_SUM_RESULT <= unsigned(i_a) + unsigned(i_b);       rs_SUM_RESULT <= signed(i_a) + signed(i_b);          cease if;          stop procedure p_SUM;       -- Purpose: Subtract two numbers.  Does both the signed and unsigned   -- subtraction for demonstration.  This process is synthesizable.   p_SUB : process (i_clk, i_rst_l)   begin      if i_rst_l = '0' and then             -- asynchronous reset (active low)       rs_SUB_RESULT <= (others => '0');       ru_SUB_RESULT <= (others => '0');     elsif rising_edge(i_clk) and then                  ru_SUB_RESULT <= unsigned(i_a) - unsigned(i_b);       rs_SUB_RESULT <= signed(i_a) - signed(i_b);          end if;          end process p_SUB;  end comport;        

Testbench:

library ieee; apply ieee.std_logic_1164.all;  entity example_signed_unsigned_tb is terminate example_signed_unsigned_tb;  architecture conduct of example_signed_unsigned_tb is    --Registers   point r_CLK   : std_logic                    := '0';   betoken r_RST_L : std_logic                    := '0';   signal r_A     : natural                      := 0;   signal r_B     : natural                      := 0;   bespeak r_A_SLV : std_logic_vector(4 downto 0) := (others => '0');   signal r_B_SLV : std_logic_vector(4 downto 0) := (others => '0');    constant c_CLK_PERIOD : time := 10 ns;    component example_signed_unsigned is     port (       i_rst_l        : in  std_logic;       i_clk          : in  std_logic;       i_a            : in  std_logic_vector(four downto 0);       i_b            : in  std_logic_vector(4 downto 0)       );   stop component example_signed_unsigned;  begin      i_DUT: example_signed_unsigned     port map (      i_rst_l          => r_RST_L,      i_clk            => r_CLK,      i_a              => r_A_SLV,      i_b              => r_B_SLV      );       clk_gen : process is   begin     r_CLK <= '0' after c_CLK_PERIOD/two, 'ane' afterwards c_CLK_PERIOD;     look for c_CLK_PERIOD;   finish procedure clk_gen;     procedure   begin          r_RST_L <= '0';     wait for 20 ns;     r_RST_L <= '1';     wait for 20 ns;      r_A_SLV <= "01001";     r_B_SLV <= "00110";        wait for xx ns;      r_A_SLV <= "10001";     r_B_SLV <= "00110";     look for xx ns;      r_A_SLV <= "10001";     r_B_SLV <= "00001";     wait for 20 ns;      r_A_SLV <= "10001";     r_B_SLV <= "00010";     wait for xx ns;          r_A_SLV <= "11111";     r_B_SLV <= "00001";     expect for twenty ns;      r_A_SLV <= "00000";     r_B_SLV <= "00001";     wait for xx ns;         wait;        end procedure;  end deport;        

Modelsim simulation moving ridge output Values Shown in HEX

Modelsim simulation wave output Values Shown in DECIMAL

Compare the two modelsim screenshots above. In the first you can see that the results of the mathematical functions are exactly the same when represented in hex. It's the interpretation of the results that is unlike. This tin can be seen by looking at the bottom screenshot. When Modelsim displays the results in decimal it interprets some of them equally negative numbers. When using signed and unsigned types you lot must be very careful! Hopefully yous understand this topic a little better. I feel similar this is an area that many digital designers struggle with, so if there is something that you do not fully understand please send me an e-mail via the Contact Link on the Sidebar and I will endeavour to go far clearer.

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